Phase-change memory device and method of fabricating the same

ABSTRACT

A phase-change memory device includes a lower electrode; and at least two phase-change memory cells sharing the lower electrode. Another phase-change memory device includes a heating layer having a smaller contact area with a phase-change material layer and a greater contact area with a PN diode structure.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a Divisional Application of U.S. patentapplication Ser. No. 12/334,385, filed Dec. 12, 2008, which claimspriority of Korean patent application number 10-2008-0031473, filed onApr. 4, 2008, which is incorporated herein by reference in its entirety.

BACKGROUND

The disclosure relates to a nonvolatile memory device, and moreparticularly, to a phase-change nonvolatile memory device using aphase-change material and a method of fabricating the same.

Recently, a Phase-change Random Access Memory (PRAM) device has beenproposed as a nonvolatile semiconductor memory device. A unit memorycell of a phase-change memory device uses a phase-change material as adata storage medium. The phase-change material has two stable phases(e.g.,, an amorphous phase and a crystalline phase) depending on theheat supplied thereto. A known phase-change material is a Ge—Sb—Te (GST)compound that is a mixture of germanium (Ge), antimony (Sb), andTellurium (Te).

If the phase-change material is heated for a short time at a temperatureclose to its melting temperature (Tm) and is then cooled quickly, thephase-change material changes from the crystalline phase into theamorphous phase. On the contrary, if the phase-change material is heatedfor a long time at a crystallization temperature lower than the meltingtemperature and is then cooled slowly, the phase-change material changesfrom the amorphous phase to the crystalline phase. The phase-changematerial has a higher resistivity in the amorphous phase than in thecrystalline phase. Thus, whether data stored in a phase-change memorycell is logical ‘1’ or logical ‘0’ can be determined by detecting acurrent flowing through the phase-change material.

Heat is supplied to effect a phase-change in the phase-change material.For example, a current is supplied to an electrode connected with thephase-change material, so that heat is generated from the electrode andsupplied to the phase-change material. The temperature caused by theheat supplied to the phase-change material varies depending on thesupplied current.

Thus, one of the most important factors in development of ahigh-integration phase-change memory device is to supply a sufficientcurrent to an electrode connected with a phase-change material, that is,an operation current (e.g., a program (write) current or an erasecurrent). To this end, a method has been proposed to use a PN diode as aswitching device of the phase-change memory device. A PN diode allows ahigher integration ratio of the phase-change memory device and increasesthe operation current in comparison with a Metal-Oxide-Semiconductor(MOS) transistor or a bipolar transistor.

FIG. 1A is a schematic plan view of a known phase-change memory deviceusing a PN diode. FIG. 1B is a cross-sectional view of the phase-changememory device taken along line X-X′ of FIG. 1A.

Referring to FIGS. 1A and 1B, the known phase-change memory deviceincludes: a substrate 11 having a device isolation region (not numbered)and an active region 12, a lower electrode 13 having a PN diodestructure including a stack of an N-type silicon layer 13A and a P-typesilicon layer 13B on the substrate 11 of the active region 12, aninsulating layer 14 covering the lower electrode 13 and burying aheating layer 15, a phase-change material layer 16 disposed on theinsulating layer 14 to contact the heating layer 15, and an upperelectrode 17 disposed on the phase-change material layer 16. The heatinglayer 15 is plug-shaped, and a program region 18 of a hemispheric shapeis formed in the phase-change material layer 16 in contact with theheating layer 15.

The size of the phase-change memory device is desirably reduced for highintegration and low power consumption of the phase-change memory device.However, a sufficiently high operation current is required becausehigh-temperature heat should be generated to change the phase of thephase-change material layer 16. Accordingly, there is a limit inreducing the size of the lower electrode 13 (i.e., the size of the PNdiode) that controls the operation current.

Accordingly, a method has been proposed to reduce the operation currentof the phase-change memory device with the above-described structure byreducing the contact area between the heating layer 15 and thephase-change material layer 16 by reducing the size of the heating layer15. This method can generate high-temperature heat even in the event ofa decrease in the operation current, because the resistance of theheating layer 15 increases with a decrease in the contact area betweenthe phase-change material layer 16 and the heating layer 15.

However, the known method uses an expensive fine patterning technology(e.g., a photolithography process using an ArF exposure source) to formthe heating layer 15. This increases the fabrication cost of thephase-change memory device. Moreover, the fine patterning technology hasa limitation in that it is difficult to increase the integration ratioof the phase-change memory device.

SUMMARY

In accordance with one or more embodiments, a phase-change memory devicecomprises: a lower electrode; and at least two phase-change memory cellssharing the lower electrode.

In accordance with one or more embodiments, a method of fabricating aphase-change memory device comprises: forming a lower electrodecomprising a PN diode structure including a junction of an N-typeconductive layer and a P-type conductive layer; forming a plurality ofheating elements on an upper one of the P-type conductive layer and theN-type conductive layer; selectively etching the upper one of the P-typeconductive layer and the N-type conductive layer between the heatingelements; forming a separated phase-change material layer on each of theheating elements; and forming a separated upper electrode on eachphase-change material layer.

In accordance with one or more embodiments, a method of fabricating aphase-change memory device comprises: forming a lower electrodecomprising a PN diode structure on an active region of a substrate;forming a heating layer on the PN diode structure; forming aphase-change material layer on the heating layer; and forming an upperelectrode on the phase-change material layer; wherein a contact areabetween the phase-change material layer and the heating layer is formedto be smaller than that between the heating layer and the PN diodestructure.

In accordance with one or more embodiments, a phase-change memory devicecomprises: a substrate having thereon an active region; a lowerelectrode comprising a PN diode structure on the active region of thesubstrate; a heating layer on the PN diode structure; a phase-changematerial layer on the heating layer; and an upper electrode on thephase-change material layer; wherein a contact area between thephase-change material layer and the heating layer is smaller than thatbetween the heating layer and the PN diode structure.

BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments are illustrated by way of example, and not bylimitation, in the figures of the accompanying drawings, whereinelements having the same reference numeral designations represent likeelements throughout.

FIG. 1A is a schematic plan view of a known phase-change memory deviceusing a PN diode.

FIG. 1B is a cross-sectional view of the phase-change memory devicetaken along line X-X′ of FIG. 1A.

FIG. 2A is a schematic plan view of a phase-change memory device inaccordance with a first embodiment.

FIG. 2B is a cross-sectional view of the phase-change memory taken alongline X-X′ of FIG. 2A.

FIGS. 3A to 3C are schematic views that illustrate a method offabricating a phase-change memory device in accordance with a firstembodiment.

FIG. 4A is a schematic plan view of a phase-change memory device inaccordance with a second embodiment.

FIG. 4B is a cross-sectional view of the phase-change memory devicetaken along line A-A′ of FIG. 4A.

FIG. 4C is a cross-sectional view of the phase-change memory devicetaken along line B-B′ of FIG. 4A.

FIGS. 5A to 5C are schematic plan views showing a comparison among thecontact area between a phase-change material layer and a heating layerof the known phase-change memory device, the contact area between aphase-change material layer and a heating layer of the phase-changememory device in accordance with the first embodiment, and the contactarea between a phase-change material layer and a heating layer of thephase-change memory device in accordance with the second embodiment.

FIG. 6A is a schematic plan view of a phase-change memory device inaccordance with a third embodiment.

FIG. 6B is a cross-sectional view of the phase-change memory devicetaken along line X-X′ of FIG. 6A.

FIGS. 7A to 7H are schematic views that illustrate a method offabricating a phase-change memory device in accordance with a thirdembodiment.

FIG. 8A is a schematic plan view of a phase-change memory device inaccordance with a fourth embodiment.

FIG. 8B is a cross-sectional view of the phase-change memory devicetaken along line A-A′ of FIG. 8A.

FIG. 8C is a cross-sectional view of the phase-change memory devicetaken along line B-B′ of FIG. 8A.

FIG. 9 is a perspective view for describing the operation principles ofthe phase-change memory devices in accordance with the third and fourthembodiments.

DESCRIPTION OF EMBODIMENTS

In the figures, the dimensions of layers and regions are exaggerated forclarity of illustration. It will also be understood that when a layer(or film) is referred to as being ‘on’ another layer or substrate, itcan be directly on the other layer or substrate, or intervening layersmay also be present. Further, it will be understood that when a layer isreferred to as being ‘under’ another layer, it can be directly under theother layer, or one or more intervening layers may also be present. Inaddition, it will also be understood that when a layer is referred to asbeing ‘between’ two layers, it can be the only layer between the twolayers, or one or more intervening layers may also be present.

FIG. 2A is a schematic plan view of a phase-change memory device inaccordance with a first embodiment. FIG. 2B is a cross-sectional view ofthe phase-change memory taken along line X-X′ of FIG. 2A.

Referring to FIGS. 2A and 2B, a phase-change memory device in accordancewith a first embodiment includes: a substrate 21 having a deviceisolation region (not numbered) and an active region 22, a firstinsulating layer 24 covering the substrate 21, a lower electrode 23disposed on the substrate 21 of the active region 22 in the firstinsulating layer 24 and having a PN diode structure; a heating layer 25disposed on the lower electrode 23 in the first insulating layer 24, asecond insulating layer 28 buried in the heating layer 25, aphase-change material layer 26 disposed to cover the heating layer 25and an upper electrode 27 disposed on the phase-change material layer26. Herein, a reference numeral 29 denotes a program region that isdisposed in the phase-change material layer 26.

The substrate 21 may be a silicon (Si) substrate.

The active region 22 may be formed in a bar type or a line type. Forexample, the active region 22 may be an impurity layer that is formed bydoping a silicon substrate with impurities. In some embodiments, theactive layer 22 is formed of an N-type impurity layer that is doped withN-type impurities such as phosphor (P) or arsenic (As). This is toreduce the potential barrier between the lower electrode 23 (i.e., thePN diode) and the active region 22 acting as one of a word line and abit line, thus increasing the electrical conductivity therebetween.Herein, the remaining region of the substrate 21 outside the activeregion 22 is referred to as the device isolation region.

The lower electrode 23 has a PN diode structure that includes a junctionof an N-type conductive layer 23A disposed on the active region 22 ofthe substrate 21 and a P-type conductive layer 23B disposed on theN-type conductive layer 23A. The N-type conductive layer 23A and theP-type conductive layer 23B may be a silicon layer, and the siliconlayer may include a polysilicon (poly-Si) layer and/or an epitaxialsilicon layer. For example, the N-type conductive layer 23A may be anN-type silicon layer doped with N-type impurities, and the P-typeconductive layer 23B may be a P-type silicon layer doped with P-typeimpurities. The N-type impurities may be phosphor (P) or arsenic (As),and the P-type impurities may be boron (B).

In some embodiments, the lower electrode 23 is formed in such a way thatthe impurity doping concentration of the N-type conductive layer 23A islower than the impurity doping concentration of the P-type conductivelayer 23B. The reason for this is that the potential barrier between theN-type conductive layer 23A and the P-type conductive layer 23B becomeslow if the impurity doping concentration of the N-type conductive layer23A is higher than the impurity doping concentration of the P-typeconductive layer 23B. If the potential barrier between the N-typeconductive layer 23A and the P-type conductive layer 23B is low, thethreshold voltage of the PN diode becomes low and thus data may bewritten in an undesired phase-change memory cell by a high voltage ofthe wordline (i.e., the active region) in a stand-by mode. This problemcan be avoided or at least reduced, by increasing the threshold voltageof the PN diode by forming the lower electrode 23 in such a way thatthat the impurity doping concentration of the N-type conductive layer23A is lower than the impurity doping concentration of the P-typeconductive layer 23B.

The heating layer 25 and the upper electrode 27 may be formed of a metalmaterial or a metal-compound material. The metal material may betitanium (Ti), tungsten (W), copper (Cu), or aluminum (Al). Themetal-compound material may be titanium nitride (TiN), tungsten nitride(WN), titanium aluminum nitride (TiAIN), or titanium tungsten (TiW).

Also, the contact area between the phase-change material layer 26 andthe heating layer 25 can be controlled according to the depositionthickness of the heating layer 25. Thus, the operation current of thephase-change memory device can be controlled according to the depositionthickness of the heating layer 25. For reference, the known methodcontrols the size of the plug-type heating layer 15 by an etchingprocess through patterning, thus making it difficult to reduce thecontact area between the phase-change material layer 16 and theplug-type heating layer 15. However, the contact area between thephase-change material layer 26 and the heating layer 25 can becontrolled by controlling the deposition thickness of the heating layer25 in accordance with the first embodiment not by an etching processthrough patterning, but by a layer growth/deposition process, thusmaking it possible to control the contact area between the phase-changematerial layer 26 and the heating layer 25 more easily.

The phase-change material layer 26 may be formed of a chalcogencompound. The chalcogen compound for the phase-change material layer 26includes at least one of Germanium-antimony-tellurium (Ge—Sb—Te),arsenic-antimony-tellurium (As—Sb—Te), strontium-antimony-tellurium(Sn—Sb—Te), strontium-indium-tellurium (Sn—In—Sb—Te),arsenic-germanium-antimony-tellurium (As—Ge—Sb—Te), Group 5A element(including tantalum (Ta), niobium (Nb) and vanadium(V))-antimony-tellurium (Group 5A element-Sb—Te), Group 6A element(including tungsten (W), molybdenum (Mo) and chrome(Cr))-antimony-tellurium (Group 6A element-Sb—Te), Group 5Aelement-antimony-selenium (Group 5A element-Sb—Se), and Group 6Aelement-antimony-selenium (Group 6A element-Sb—Se). In some embodiments,the phase-change material layer 26 is formed of a Ge—Sb—Te (GST)compound.

The first insulating layer 24 and the second insulating layer 28 may beformed of at least one selected from the group consisting of an oxidelayer, a nitride layer, an oxynitride layer, and a stack thereof. Theoxide layer may include silicon oxide (SiO₂), Boron Phosphorus SilicateGlass (BPSG), Phosphorus Silicate Glass (PSG), Tetra Ethyle OrthoSilicate (TEOS), Un-doped Silicate Glass (USG), Spin On Glass (SOG),High Density Plasma (HDP), or Spin On Dielectric (SOD). The nitridelayer may include silicon nitride (Si₃N₄). The oxynitride layer mayinclude silicon oxynitride (SiON).

In the configuration specifically depicted in FIG. 2B, the heating layer25 is formed in a cup shape in the phase-change memory device inaccordance with the first embodiment, thereby making it possible toreduce the contact area, which is annular in shape in the specificallyillustrated configuration, between the phase-change material layer 26and the heating layer 25. Accordingly, the size of the program region 29can be considerably reduced, thus making it possible to reduce the heatneeded to be supplied to the program region 29. It should be noted thatother arrangements are not excluded. For example, the contact areabetween the heating layer 25 and the phase-change material layer 26 isnot necessarily annular, or the heating layer 25 is not necessarilycup-shaped; it can be cylindrical or tubular instead.

Also, the contact area between the phase-change material layer 26 andthe heating layer 25 can be controlled by controlling the depositionthickness of the heating layer 25 as will be described herein below.Thus, the contact area between the heating layer 25 and the phase-changematerial layer 26 can be reduced even without the use of an expensivefine patterning technology, thereby making it possible to reduce thefabrication cost of the phase-change memory device.

FIGS. 3A to 3C are schematic views that illustrate a method offabricating a phase-change memory device in accordance with a firstembodiment.

Referring to FIG. 3A, impurities are ion-implanted into a substrate 21to form an active region 22. The impurities may be P-type impurities orN-type impurities. The P-type impurities may be boron (B), and theN-type impurities may be arsenic (As) or phosphor (P). In someembodiments the ion implantation process is performed using N-typeimpurities. This is to reduce the potential barrier between the activeregion 22 and a lower electrode 23 (i.e., a PN diode), which is to beformed through the subsequent process, thus increasing the electricalconductivity therebetween.

A predetermined region of the substrate 21 is etched to form a trench(not illustrated) for device isolation, and the trench is filled with aninsulating layer to form a device isolation region (not illustrated).The trench may be formed in a line type or a bar type although otherarrangements are not excluded. The remaining region of the substrate 21except the device isolation region is defined as the active region 22,and the active region 22 has a line type or a bar type due to the linetype or bar type of the device isolation region.

A lower electrode 23 with a PN diode structure is formed on thesubstrate 21 of the active region 22. The lower electrode 23 with a PNdiode structure may be formed of a stack of an N-type conductive layer23A and a P-type conductive layer 23B that are sequentially stacked onthe active region 22 of the substrate 21. In some embodiments, the lowerelectrode 23 is formed in such a way that the impurity dopingconcentration of the N-type conductive layer 23A is lower than theimpurity doping concentration of the P-type conductive layer 23B. Thereason for this is that, if the impurity doping concentration of theN-type conductive layer 23A is lower than the impurity dopingconcentration of the P-type conductive layer 23B, the potential barrierbetween the N-type conductive layer 23A and the P-type conductive layer23B can be increased to increase the threshold voltage of the PN diode.For reference, the high threshold voltage of a PN diode can prevent anoise-caused malfunction of the PN diode.

The N-type conductive layer 23A and the P-type conductive layer 23B maybe formed of a silicon layer, and the silicon layer may include apolysilicon layer or an epitaxial silicon layer. For example, the N-typeconductive layer 23A may be formed of an N-type silicon layer doped withN-type impurities, and the P-type conductive layer 23B may be formed ofa P-type silicon layer doped with P-type impurities.

For example, the P-type silicon layer may be formed by ion-implantingP-type impurities in situ during the formation of a polysilicon layerthrough a Chemical Vapor Deposition (CVD) process or a Physical VaporDeposition (PVD) process, or by ion-implanting P-type impurities afterthe formation of the polysilicon layer. Also, the P-type silicon layermay be formed by ion-implanting P-type impurities in situ during theformation of an epitaxial silicon layer through an epitaxial growthprocess, or by ion-implanting P-type impurities after the formation ofthe epitaxial silicon layer. Also, the P-type silicon layer may beformed by counter-doping P-type impurities into an N-type silicon layer.

A first insulating layer 24 is formed over the resulting structureincluding the lower electrode 23. The first insulating layer 24 may beformed of at least one selected from the group consisting of an oxidelayer, a nitride layer, an oxynitride layer, and a stack thereof.

A photoresist pattern (not illustrated) is formed on the firstinsulating layer 24. Using the photoresist pattern as an etch barrier,the first insulating layer 24 is etched to form an open region 30 thatexposes the top of the P-type conductive layer 23B.

The open region 30 is a region where a heating layer is to be formedthrough the subsequent process. In the case of the known plug-typeheating layer 15, the open region has to be formed with a small width inorder to reduce the contact area between the phase-change material layer16 and the heating layer 15. Therefore, the known method has to form theopen region by an expensive fine patterning technology (e.g., aphotolithographic etching process using an ArF exposure source), thusincreasing the fabrication cost of the phase-change memory device.However, as will be described herein below, the contact area between thephase-change material layer 26 and the heating layer 25 can be reducedeven without having to form the open region 30 to have a small width.Thus, the open region 30 can be formed by an etching process using aninexpensive patterning technology, thereby making it possible to reducethe fabrication cost of the phase-change memory device.

Referring to FIG. 3B, a conductive layer for a heating layer is formed,e.g., by a deposition process, over the first insulating layer 24including the open region 30. The conductive layer for the heating layermay be formed of a metal material or a metal-compound material. Themetal material may be titanium (Ti), tungsten (W), copper (Cu), oraluminum (Al). The metal-compound material may be titanium nitride(TiN), tungsten nitride (WN), titanium aluminum nitride (TiAIN), ortitanium tungsten (TiW). The contact area between a heating layer 25 anda phase-change material layer 26, which are to be formed through thesubsequent processes, may be controlled according to the depositionthickness of the conductive layer for the heating layer.

A second insulating layer 28 is formed to fill a remaining empty spacein the open region 30 after the formation, e.g., deposition, of theconductive layer for the heating layer has been completed. The secondinsulating layer 28 may be formed of at least one selected from thegroup consisting of an oxide layer, a nitride layer, an oxynitridelayer, and a stack thereof.

The second insulating layer 28 and the conductive layer for the heatinglayer are planarized to expose the top of the first insulating layer 24,thereby forming a heating layer 25. The planarization process may beperformed using a Chemical Mechanical Polishing (CMP) process or anetch-back process.

Referring to FIG. 3C, a phase-change material layer 26 and an upperelectrode 27 are formed on the first insulating layer 24 and the secondinsulating layer 28 to cover the heating layer 25. The upper electrode27 may be formed of the same material as the heating layer 25. That is,the upper electrode 27 may be formed of a metal material or ametal-compound material. The phase-change material layer 26 may beformed using a chalcogen compound such as a Germanium-antimony-tellurium(Ge—Sb—Te, GST) compound.

Although not illustrated in the drawings, a passivation layer is formedin some embodiments on the first insulating layer 24 to cover the upperelectrode 27, and a predetermined region of the passivation layer isopened to form an interconnection contact hole and an interconnection,thereby completing the fabrication of the phase-change memory device.

In the description above, the heating layer 25 is formed in a cup shapein the phase-change memory device in accordance with the firstembodiment, thereby making it possible to reduce the contact areabetween the phase-change material layer 26 and the heating layer 25 evenwithout the use of an expensive fine patterning technology. Accordingly,it is possible to reduce the fabrication cost of the phase-change memorydevice.

Hereinafter, a description will be given of a phase-change memory deviceand a method of fabricating the same in accordance with a secondembodiment, which can further reduce the contact area between aphase-change material layer and a heating layer in comparison with thefirst embodiment. For the sake of simplicity, a detailed description ofthe common features between the second embodiment and the firstembodiment will be omitted and the following description will focus onthe differences between the first and second embodiments.

FIG. 4A is a schematic plan view of a phase-change memory device inaccordance with a second embodiment. FIG. 4B is a cross-sectional viewof the phase-change memory device taken along line A-A′ of FIG. 4A. FIG.4C is a cross-sectional view of the phase-change memory device takenalong line B-B′ of FIG. 4A.

Referring to FIGS. 4A to 4C, a phase-change memory device in accordancewith a second embodiment includes a substrate 31 having a deviceisolation region (not numbered) and an active region 32, a firstinsulating layer 34 covering the substrate 31, a lower electrode 33disposed on the substrate 31 of the active region 32 in the firstinsulating layer 34 and having a PN diode structure, a heating layer 35disposed on the lower electrode 33 in the first insulating layer 34, aphase-change material layer 36 disposed to cover a portion of theheating layer 35 and an upper electrode 37 disposed on the phase-changematerial layer 36. The heating layer 35 may be formed in a cup type 35Aor a plug type 35B. If the heating layer 35 is formed in the cup type35A, the phase-change memory device may further include a secondinsulating layer 38 buried in the heating layer 35A. A reference numeral39 denotes a program region that is disposed in the phase-changematerial layer 36.

In the description above, the phase-change material layer 36 is disposedto contact only a portion of the exposed top of the heating layer 35 inthe phase-change memory device in accordance with the second embodiment,thereby making it possible to further reduce the contact area betweenthe heating layer 35 and the phase-change material layer 36, as will bedescribed below with reference to FIGS. 5A to 5C.

FIGS. 5A to 5C are schematic plan views showing a comparison among thecontact area between the phase-change material layer and the heatinglayer of the known phase-change memory device (see FIG. 5A), the contactarea between the phase-change material layer and the heating layer ofthe phase-change memory device in accordance with the first embodiment(see FIG. 5B), and the contact area between the phase-change materiallayer and the heating layer of the phase-change memory device inaccordance with the second embodiment (see FIG. 5C).

Referring to FIGS. 5A to 5C, it can be seen that the contact area A2between the phase-change material layer 26 and the cup-type heatinglayer 25 in accordance with the first embodiment is smaller than thecontact area Al between the phase-change material layer 16 and the knownplug-type heating layer 15 (A1>A2).

Also, it can be seen that the contact area A3 between the phase-changematerial layer 36 and the plug-type heating layer 35B in accordance withthe second embodiment is smaller than the contact area Al between thephase-change material layer 16 and the known plug-type heating layer 15(A1>A3). Also, it can be seen that the contact area A4 between thephase-change material layer 36 and the cup-type heating layer 35A inaccordance with the second embodiment is considerably smaller than thecontact area Al between the phase-change material layer 16 and the knownplug-type heating layer 15 (A1>A4).

Also, it can be seen that the contact area A4 between the phase-changematerial layer 36 and the cup-type heating layer 35A in accordance withthe second embodiment is smaller than the contact area A2 between thephase-change material layer 26 and the cup-type heating layer 25 inaccordance with the first embodiment (A2>A4).

In the description above, the phase-change material layer 36 is disposedto cover only a portion, not the entirety, of the exposed top of theheating layer 35 in the phase-change memory device in accordance withthe second embodiment thereby making it possible to further reduce thecontact area between the heating layer 35 and the phase-change materiallayer 36 in comparison with the first embodiment. Accordingly, it ispossible to further reduce the operation current of the phase-changememory device.

A method of fabricating the phase-change memory device in accordancewith the second embodiment can be easily derived from the method offabricating the phase-change memory device in accordance with the firstembodiment, which has been described with reference to FIGS. 3A to 3C,and thus its detailed description will be omitted for conciseness.

Hereinafter, a description will be given of a phase-change memorydevices and a method of fabricating the same in accordance with thirdand fourth embodiments, which can reduce the contact area between aheating layer and a phase-change material layer, thereby making itpossible to provide a high-integration phase-change memory device whilereducing the operation current thereof. To this end, the phase-changememory devices in accordance with the third and fourth embodiments areconfigured in such a way that two phase-change memory cells share onelower electrode. The lower electrode includes a PN diode, and eachphase-change memory cell includes a heating layer, a phase-changematerial layer, and an upper electrode. For the sake of convenience, adetailed description of the common features between the third/fourthembodiment and the first/second embodiment will be omitted and thefollowing description will focus on the differences between theembodiments.

FIG. 6A is a schematic plan view of a phase-change memory device inaccordance with a third embodiment. FIG. 6B is a cross-sectional view ofthe phase-change memory device taken along line X-X′ of FIG. 6A.

Referring to FIGS. 6A and 6B, a phase-change memory device in accordancewith a third embodiment includes a substrate 41 having a deviceisolation region (not numbered) and an active region 42, a firstinsulating layer 44 covering the substrate 41, a lower electrode 43disposed on the active region 42 and having a shared region and twoisolated regions, and two phase-change memory cell 53 each disposed onone of the isolated regions of the lower electrode 43. Each phase-changememory cell 53 includes a heating layer 45 disposed on the respectiveisolated region of the lower electrode 43, a phase-change material layer46 disposed to cover the heating layer 45, and an upper electrode 47disposed on the phase-change material layer 46. The phase-change memorydevice may further include a second insulating layer 48 buried betweenthe isolated regions of the lower electrode 43 and the heating layer 45.A reference numeral 49 denotes a program region that is disposed in thephase-change material layer 46.

The shared region in the lower electrode 43 is formed of an

N-type conductive layer 43A, and the isolated region in the lowerelectrode 43 is formed of a junction of the N-type conductive layer 43Aand a P-type conductive region 43B. That is, the lower electrode 43includes multiple, at least two, PN diodes each of which has a junctionof the N-type conductive layer 43A and the P-type conductive layer 43Bin the respective isolated region, and multiple, at least two,phase-change memory cells 53 share the N-type conductive layer 43A. TheP-type conductive layer 43B is electrically connected with therespective phase-change memory cell 53.

The heating layer 45 may have a plug shape or a cup-shape. Otherarrangements are, however, not excluded.

In the description above, two phase-change memory cells 53 share onelower electrode 43 in the phase-change memory device in accordance withthe third embodiment, thus making it possible to considerably increasethe integration ratio of the phase-change memory device. That is, thethird embodiment can increase the integration ratio of the phase-changememory device two or more times in comparison with the first and secondembodiments.

Also, the third embodiment can increase the integration ratio of thephase-change memory device and can also reduce the contact area betweenthe phase-change material layer 46 and the heating layer 45, therebymaking it possible to reduce the required operation current of thephase-change memory device as will be discussed in the followingdescription of a method of fabricating the phase-change memory device inaccordance with the third embodiment, with reference to FIGS. 7A to 7H.

FIGS. 7A to 7H are schematic views that illustrate a method offabricating a phase-change memory device in accordance with a thirdembodiment. FIGS. 7A, 7C, 7E and 7G are schematic plan views and FIGS.7B, 7D, 7F and 7H are cross-sectional views taken along line X-X′ of theplan views, respectively.

Referring to FIGS. 7A and 7B, impurities are ion-implanted into asubstrate 41 to form an active region 42. The impurities may be P-typeimpurities or N-type impurities. The P-type impurities may be boron (B),and the N-type impurities may be arsenic (As) or phosphor (P). In someembodiments the ion implantation process is performed using N-typeimpurities. This is to reduce the potential barrier between the activeregion 42 and the lower electrode 43, which is to be formed through thesubsequent process, thus increasing the electrical conductivitytherebetween.

A predetermined region of the substrate 41 is etched to form a trench(not illustrated) for device isolation, and the trench is filled with aninsulating layer to form a device isolation region (not illustrated).The trench may be formed in a line type or a bar type although otherarrangements are not excluded. The remaining region of the substrate 41outside the device isolation region is defined as the active region 42,and the active region 42 has a line type or a bar type due to the linetype or bar type of the device isolation region.

A lower electrode 43 with a PN diode structure is formed on the activeregion 42. The PN diode structure may be formed of a stack of an N-typeconductive layer 43A and a P-type conductive layer 43B that aresequentially stacked on the active region 42 of the substrate 41. Insome embodiments, the lower electrode 43 is formed in such a way thatthe impurity doping concentration of the N-type conductive layer 43A islower than the impurity doping concentration of the P-type conductivelayer 43B. The reason for this is that the threshold voltage of the PNdiode can be increased if the impurity doping concentration of theN-type conductive layer 43A is lower than the impurity dopingconcentration of the P-type conductive layer 43B. For reference, thehigh threshold voltage of a PN diode can prevent a noise-causedmalfunction of the PN diode.

The N-type conductive layer 43A and the P-type conductive layer 43B maybe formed of a silicon layer, and the silicon layer may include apolysilicon layer or an epitaxial silicon layer. For example, the N-typeconductive layer 43A may be formed of an N-type silicon layer doped withN-type impurities, and the P-type conductive layer 43B may be formed ofa P-type silicon layer doped with P-type impurities.

For example, the P-type silicon layer may be formed by ion-implantingP-type impurities in situ during the formation of a polysilicon layerthrough a Chemical Vapor Deposition (CVD) process or a Physical VaporDeposition (PVD) process, or by ion-implanting P-type impurities afterthe formation of the polysilicon layer. Also, the P-type silicon layermay be formed by ion-implanting P-type impurities in situ during theformation of an epitaxial silicon layer through an epitaxial growthprocess, or by ion-implanting P-type impurities after the formation ofthe epitaxial silicon layer. Also, the P-type silicon layer may beformed by counter-doping P-type impurities into an N-type silicon layer.

A first insulating layer 44 is formed over the resulting structureincluding the lower electrode 43. The first insulating layer 44 may beformed of at least one selected from the group consisting of an oxidelayer, a nitride layer, an oxynitride layer, and a stack thereof.

A photoresist pattern (not illustrated) is formed on the firstinsulating layer 44. Using the photoresist pattern as an etch barrier ormask, the first insulating layer 44 is etched to form an open region 50that exposes the top of the P-type conductive layer 43B.

The open region 50 is a region where a heating layer is to be formedthrough the subsequent process. In the case of the known plug-typeheating layer, the open region has to be formed to have a small width inorder to reduce the contact area between the phase-change material layer16 and the heating layer 15. Therefore, the known method forms the openregion by an expensive fine patterning technology (e.g., aphotolithographic etching process using an ArF exposure source), thusincreasing the fabrication cost of the phase-change memory device.However, since the heating layer 45 can be formed in a cylindricalshape, as will be discussed herein below, and/or the size of the heatinglayer 45 can be reduced through the subsequent process for isolating thelower electrode 43, the third embodiment can reduce the contact areabetween the phase-change material layer 46 and the heating layer 45 evenwithout having to form the open region 50 to have a small width. Thus,the open region 50 can be formed by an etching process using aninexpensive patterning technology, thereby making it possible to reducethe fabrication cost of the phase-change memory device.

Referring to FIGS. 7C and 7D, a conductive layer 51 for a heating layeris formed over the first insulating layer 44 including the open region50. The conductive layer 51 for the heating layer may be formed of ametal material or a metal-compound material. The metal material may betitanium (Ti), tungsten (W), copper (Cu), or aluminum (Al). Themetal-compound material may be titanium nitride (TiN), tungsten nitride(WN), titanium aluminum nitride (TiAIN), or titanium tungsten (TiW). Thecontact area between a heating layer and a phase-change material layer,which are to be formed through the subsequent processes, may becontrolled according to the deposition thickness of the conductive layer51 for the heating layer.

A blanket etching process, for example, an etch-back process isperformed such that the conductive layer 51 for the heating layerremains only on the sidewall of the open region 50. That is, theremaining conductive layer 51 of the heating layer has a cylindricalshape. Alternatively, unwanted portions of the conductive layer 51 forthe heating layer can be removed later during the process(es) of formingthe isolated regions as discussed herein below.

Referring to FIGS. 7E and 7F, a line-type photoresist pattern 52 isformed on the first insulating layer 44 to expose some or all of theempty space in the open region 50 after the formation of the conductivelayer 51 for the heating layer. The photoresist pattern 52 may be formedin some embodiments perpendicular to the line-type active region 42. Aportion of the conductive layer 51 remaining on the sidewall of the openregion 50 is also exposed by the photoresist pattern 52.

Using the photoresist pattern 52 as an etch barrier or mask, the P-typeconductive layer 43B of the exposed lower electrode 43 and the exposedconductive layer 51 for the heating layer are etched to form a heatinglayer 45 and also form the shared and isolated regions in the lowerelectrode 43. An over-etch process may be performed to etch a portion ofthe N-type conductive layer 43A in order to completely isolate theP-type conductive layer 43B in two isolated regions of the lowerelectrode 43.

The lower electrode 43 including a shared region and two isolatedregions is formed through the above etching process. The shared regionis formed of the N-type conductive layer 43A at the bottom an expandedopen region 50A obtained as a result of the etching process as shown inFIG. 7F. The two isolated regions are formed of the isolated portions ofP-type conductive layer 43B and the underlying N-type conductive layer43A. That is, through the above etching process, the lower electrode 43may be formed such that it includes a pair of PN diodes having ajunction of the N-type conductive layer 43A and the P-type conductivelayer 43B, and the N-type conductive layers 43A of the PN diodes areconnected with each other.

Also, the heating layer 45 may have a plug shape through the aboveetching process.

The etching process for forming the heating layer 45 and the lowerelectrode 43 having the shared region and the isolated regions may beperformed using a dry etch process or a wet etch process. The dry etchprocess may be performed using the plasma of a mixture of chlorine gas(Cl₂) and argon gas (Ar), and the wet etch process may be performedusing the solution of a mixture of sulfuric acid (H₂SO₄) and peroxide(H₂O₂) or the solution of a mixture of ammonium hydroxide (NH₄OH) andperoxide (H₂O₂).

Herein, the open region 50 exposing the top of the N-type conductivelayer 43A in the shared region through the above etching process isreferred to as the expanded open region 50A.

Referring to FIGS. 7G and 7H, the photoresist pattern 52 is removed. Thephotoresist pattern 52 may be removed through a stripping process.

A second insulating layer 48 is formed to fill an empty space in theexpanded open region 50A. The second insulating layer 48 may be formedof at least one selected from the group consisting of an oxide layer, anitride layer, an oxynitride layer, and a stack thereof.

The second insulating layer 48 is planarized to expose the tops of theheating layer 45 and the first insulating layer 44. The planarizationprocess may be performed using a Chemical Mechanical Polishing (CMP)process or an etch-back process.

A phase-change material layer 46 and an upper electrode 47 are formed onthe first insulating layer 44 and the second insulating layer 48 tocover the heating layer 45. The upper electrode 47 may be formed of thesame material as the heating layer 45. That is, the upper electrode 47may be formed of a metal material or a metal-compound material. Thephase-change material layer 46 may be formed using a chalcogen compoundsuch as a Germanium-antimony-tellurium (Ge—Sb—Te, GST) compound.

Through the above processes, the phase-change memory device can beformed such that two phase-change memory cells 53 share one lowerelectrode 43.

Although not illustrated in the drawings, a passivation layer is formedin some embodiments on the first insulating layer 44 and the secondinsulating layer 48 to cover the upper electrode 47, and a predeterminedregion of the passivation layer is opened to form an interconnectioncontact hole and an interconnection, thereby completing the fabricationof the phase-change memory device.

In the description above, the phase-change memory device in accordancewith the third embodiment is formed such that multiple, at least two,phase-change memory cells 53 share one lower electrode 43, therebymaking it possible to considerably increase the integration ratio of thephase-change memory device.

FIG. 8A is a schematic plan view of a phase-change memory device inaccordance with a fourth embodiment. FIG. 8B is a cross-sectional viewof the phase-change memory device taken along line A-A′ of FIG. 8A. FIG.8C is a cross-sectional view of the phase-change memory device takenalong line B-B′ of FIG. 8A.

Referring to FIGS. 8A to 8C, a phase-change memory device in accordancewith a fourth embodiment includes a substrate 61 having a deviceisolation region and an active region 62, a first insulating layer 64covering the substrate 61, a lower electrode 63 disposed on the activeregion 62 and having a shared region and multiple isolated regions, andmultiple phase-change memory cells 71 each disposed on one of theisolated regions. Each phase-change memory cell 71 includes a heatinglayer 65 disposed on the respective isolated region, a phase-changematerial layer 66 disposed on the heating layer 65 and an upperelectrode 67 disposed on the phase-change material layer 66. Thephase-change memory device may further include a second insulating layer68 buried between the isolated regions of the lower electrode 63 and theheating layer 65. A reference numeral 69 denotes a program region thatis disposed in the phase-change material layer 66.

The shared region in the lower electrode 63 is formed of an N-typeconductive layer 63A, and each isolated region in the lower electrode 63is formed of a junction of a P-type conductive region 63B and the N-typeconductive layer 63A. That is, the lower electrode 63 includes multiplePN diodes each of which has a junction of the N-type conductive layer63A and the P-type conductive layer 63B, and multiple phase-changememory cells 71 share the N-type conductive layer 63A. The P-typeconductive layer 63B is electrically connected with the respectivephase-change memory cell 71.

The heating layer 65 may be formed of a cup-shaped heating layer 65A ora plug-type heating layer 65B or a cylindrical heating layer (not shown)as discussed with respect to FIGS. 6A and 6B. If the heating layer 65 isformed of the cup-shaped or cylindrical heating layer 65A, thephase-change memory device may further include a third insulating layer70 that fills an empty space in the heating layer 65A. The thirdinsulating layer 70 may be formed of the same material as the firstinsulating layer 64 and the second insulating layer 68. That is, thethird insulating layer 70 may be formed of at least one selected fromthe group consisting of an oxide layer, a nitride layer, an oxynitridelayer, and a stack thereof.

The phase-change material layer 66 may be formed to cover the entireheating layer 65, or may be formed to cover only a portion of theheating layer 65 in order to further reduce the contact area between thephase-change material layer 66 and the heating layer 65.

In the description above, multiple, at least two, phase-change memorycells 71 share one lower electrode 63 in the phase-change memory devicein accordance with the fourth embodiment, thus making it possible toconsiderably increase the integration ratio of the phase-change memorydevice. That is, the fourth embodiment can increase the integrationratio of the phase-change memory device two or more times in comparisonwith the first and second embodiments.

Also, the fourth embodiment can increase the integration ratio of thephase-change memory device and can also reduce the contact area betweenthe phase-change material layer 66 and the heating layer 65, therebymaking it possible to reduce the required operation current of thephase-change memory device.

A method of fabricating the phase-change memory devices in accordancewith the fourth embodiment can be easily derived from the method(s) offabricating the phase-change memory devices in accordance with the firstand/or second and/or third embodiments, and thus its detaileddescription will be omitted for conciseness.

In the phase-change memory devices in accordance with the third andfourth embodiments, the two or more adjacent phase-change memory cells(i.e., the structures including the heating layer, the phase-changematerial layer, and the upper electrode) do not interfere with eachother although they share one lower electrode. This will be describedwith reference to FIG. 9.

FIG. 9 is a perspective view for describing the operation principles ofthe phase-change memory devices in accordance with the third and fourthembodiments. FIG. 9 illustrates the phase-change memory device inaccordance with the third embodiment, and it is assumed that the activeregion 42 acts as a word line and the upper electrode 47 acts as a bitline although the roles of the active region 42 and the upper electrode47 can be reversed.

Referring to FIG. 9, a word line signal, for example, a first voltage isapplied to the active region 42 and simultaneously a bit line signal,for example, a second voltage is applied to a first upper electrode 47Ain order to write data in a phase-change material layer 46A of a firstunit cell. If the second voltage is higher than the first voltage, thelower electrode 43 (i.e., the first PN diode) of the first unit cell hasa forward state and thus an operation current flows from the first upperelectrode 47A to the active region 42. At this point, heat is generatedat the heating layer 45 by the operation current, and the phase-changematerial layer 46A of the first unit cell changes into one of anamorphous phase or a crystalline phase depending on the intensity andduration of the generated heat.

Because the first unit cell and the second unit cell share the N-typeconductive layer 43A of the lower electrode 43, that is, because thefirst unit cell and a second unit cell are electrically connected toeach other, an operation current applied to the first unit cell can flowthrough the N-type conductive layer 43A to the second unit cell.However, the operation current cannot flow to a second upper electrode47B to change the phase-change material layer 46B of the second unitcell. The reason for this is that the operation current applied to thefirst unit cell is a reverse state in the lower electrode 43 of thesecond unit cell. That is, the operation current cannot flow in thesecond unit cell because a reverse bias is applied to the second PNdiode.

In summary, although two or more adjacent phase-change memory cellsshare one lower electrode in the phase-change memory device inaccordance with the third and fourth embodiments, they do not interferewith each other.

As described above, the heating layer is formed in the phase-changememory device so that it is possible to effectively reduce the contactarea between the phase-change material layer and the heating layer.

Also, the phase-change material layer in some embodiments is formed tocover only a portion of the heating layer, thereby making it possible tofurther reduce the contact area between the phase-change material layerand the heating layer.

Accordingly, the contact area between the phase-change material layerand the heating layer can be reduced without having to use an expensivefine patterning technology (although such technology can still be usedin some embodiments if desirable), thereby making it possible to reducethe fabrication cost of the phase-change memory device.

Also, two or more phase-change memory cells can share one lowerelectrode, thereby making it possible to considerably increase theintegration ratio of the phase-change memory device.

Consequently, it is possible to reduce the required operation current ofthe phase-change memory device while increasing the integration ratio ofthe phase-change memory device.

While specific embodiments have been described, it will be apparent tothose skilled in the art that various changes and modifications may bemade.

1. A method of fabricating a phase-change memory device, the methodcomprising: forming a lower electrode comprising a PN diode structureincluding a junction of an N-type conductive layer and a P-typeconductive layer; forming a plurality of heating elements on an upperone of the P-type conductive layer and the N-type conductive layer;selectively etching the upper one of the P-type conductive layer and theN-type conductive layer between the heating elements; forming aseparated phase-change material layer on each of the heating elements;and forming a separated upper electrode on each phase-change materiallayer.
 2. The method of claim 1, wherein each heating element is formedin a plug type, a cup type or a cylinder type.
 3. The method of claim 2,wherein the heating element is formed in the plug type by: forming aninsulating layer having an open region that exposes the top of the upperone of the P-type conductive layer and the N-type conductive layer; andfilling the open region with a conductive material to obtain the heatingelement.
 4. The method of claim 2, wherein the heating element is formedin the cup type by: forming an insulating layer having an open regionthat exposes the top of the upper one of the P-type conductive layer andthe N-type conductive layer; forming a conductive layer over theinsulating layer including the open region; and removing the conductivelayer outside the open region.
 5. The method of claim 2, wherein thephase-change material layer is formed to cover only a portion of therespective heating element.
 6. The method of claim 1, wherein each ofthe N-type conductive layer and the P-type conductive layer is formed ofa silicon layer.